Generally, a semiconductor device consists of a semiconductor chip and a package encapsulating the chip. The semiconductor chip comprises a plurality of conductive pads. The pads are generally located at a peripheral area, i.e., close to the edge of the chip. The pads are used for an electrical testing of the chip during its fabrication process. Generally, a plurality of the chips is fabricated simultaneously on a semiconductor wafer. The electrical testing is performed to sort out defective chips among the plurality of the chips.
Meanwhile, the pads are also used for a packaging process. The pads are electrically connected to outputs of the semiconductor device during the packaging process. For example, each of the pads is connected to a corresponding one of output leads of the package through conductive wires.
Generally, each of the pads is used for both the electrical testing and the packaging process. In this case, it is difficult to bond the wires on the pads. This is due to damage on the pad. During the electrical testing, probing tips are physically contacted to the pads. This physical contacting induces the damage on the pads.
A semiconductor wafer, which is useful for a wafer-level burn-in testing, is disclosed in a document, Japanese laid-open patent No. 2000-124279. FIG. 1 is a plan view of the wafer disclosed in the Japanese document.
Referring to FIG. 1, a plurality of semiconductor chips 1 is arranged on a wafer. Scribe lanes 3 intervene between each of the plurality of semiconductor chips 1. A burn-in power line 4 is formed on the scribe lanes 3. The burn-in power line 4 is connected electrically to a probing pad 2. The probing pad 2 is connected electrically to internal circuitry (though not shown) of the chip through a bonding pad 7. A fuse 5 intervenes between the bonding pad 7 and the probing pad 2.
The burn-in testing of the wafer of the Japanese documentation is described hereinafter. The wafer is loaded into an oven having a selected temperature and atmosphere. Next, a burn-in voltage is applied to the burn-in power lines 4. By applying the burn-in voltage, there is electric current flowing into the chips 1. An electrical current, which is excessively large, flows into a defective chip. The excessive current makes the fuse 5 on the defective chip melt, thereby opening the fuse. That is to say, the defective chip is disconnected from the burn-in power line 4. If the defective chip were still connected to the burn-in power line 4 with the excessive current, the operating voltage would be decreased. According to the Japanese documentation, there is no decreasing in the burn-in voltage, because the defective chip is disconnected from the burn-in power line 4. Therefore, the burn-in testing can be performed under a stable condition for the other good chips. After the burn-in testing, the good chips are subject to subsequent manufacturing processes including a packaging process.
According to the Japanese documentation, the fuse of the defective chip is opened, while the fuse of the good chip remained not opened. The inventor of the present invention found that the probing pad, which is connected to the bonding pad in the good chip through the not-opened fuse, induces increased parasitic capacitance and parasitic resistance. The increased parasitic capacitance and parasitic resistance may induce a speed delay in operation, even though the chip is packaged.